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ASAHI KASEI
[AK4551]
Low Power & Small Package 20bit CODEC
AK4551
GENERAL DESCRIPTION The AK4551 is a low voltage 20bit A/D & D/A converter for portable digital audio system. In the AK4551, the loss of accuracy form clock jitter is also improved by using SCF techniques for on-chip post filter. Analog signal input/output of the AK4551 are single-ended, therefore, any external filters are not required. The AK4551 is suitable for portable digital audio system, as the AK4551 is lower power dissipation and a smaller package than AK4519. FEATURES o HPF for DC-offset cancel (fc=3.4Hz) o Single-ended ADC - S/(N+D): 82dB@VDD=2.5V - Dynamic Range, S/N: 89dB@VDD=2.5V o Single-ended DAC - Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling - S/(N+D): 85dB@VDD=2.5V - Dynamic Range, S/N: 92dB@VDD=2.5V o Audio I/F format: MSB First, 2's Compliment (AK4519 compatible) - ADC: 20bit MSB justified - DAC: 20bit LSB justified o Input/Output Voltage: 0.6 X VDD (=1.5Vpp@VDD=2.5V) o High Jitter Tolerance o Sampling Rate: 8kHz to 50kHz o Master Clock: 256fs or 384fs or 512fs o Power Supply: 2.2 to 3.6V o Low Power Supply Current: 10mA o Ta = -20 to 85C o Very Small Package: 16pin TSSOP
VDD VSS Modulator Modulator Decimation Filter Decimation Filter Serial I/O Interface Clock Divider MCLK LRCK SCLK SDTO SDTI DEM0 AOUTL LPF Modulator Modulator 8X Interpolator 8X Interpolator PWDA PWAD DEM1
AINL
AINR
VCOM
Common Voltage
AOUTR
LPF
MS0029-E-00 -1-
2000/5
ASAHI KASEI
[AK4551]
n Ordering Guide
AK4551VT AKD4551 -20 +85C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4551
n Pin Layout
VCOM AINR AINL VSS VDD DEM0 DEM1 SDTO 1 2 3 4 5 6 7 8 16 15 14 AOUTR AOUTL PWDA PWAD SCLK MCLK LRCK SDTI
Top View
13 12 11 10 9
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VCOM AINR AINL VSS VDD DEM0 DEM1 SDTO SDTI LRCK MCLK SCLK PWAD PWDA AOUTL AOUTR I/O O I I I I O I I I I I I O O Function Common Voltage Output Pin, 0.45 x VDD Rch Analog Input Pin Lch Analog Input Pin Ground Pin Power Supply Pin De-emphasis Control Pin De-emphasis Control Pin Audio Serial Data Output Pin Audio Serial Data Input Pin Input/Output Channel Clock Pin Master Clock Input Pin Audio Serial Data Clock Pin ADC Power-Down & Reset Mode Pin "L": Power down. ADC should always be reset upon power-up. DAC Power-Down & Reset Mode Pin "L": Power down. DAC should always be reset upon power-up. Lch Analog Output Pin Rch Analog Output Pin
MS0029-E-00 -2-
2000/5
ASAHI KASEI
[AK4551]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1) Parameter Power Supply Input Current (Any Pin Except Supplies) Input Voltage Ambient Temperature (power applied) Storage Temperature Note 1. All voltages with respect to ground. Symbol VDD IIN VIN Ta Tstg min -0.3 -0.3 -20 -65 max 4.6 10 VDD+0.3 85 150 Units V mA V C C
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Power Supply
Note 1. All voltages with respect to ground.
Symbol VDD
min 2.2
typ 2.5
max 3.6
Units V
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0029-E-00 -3-
2000/5
ASAHI KASEI
[AK4551]
ANALOG CHARACTERISTICS
(Ta=25C; VDD=2.5V; fs=44.1kHz; Signal Frequency=1kHz; SCLK=64fs; Measurement frequency=10Hz 20kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Analog Source Impedance=470 (Note 2) Resolution 20 Bits S/(N+D) (-0.5dB Input) 72 82 dB D-Range (-60dB Input, A-weighted) 82 89 dB S/N (A-weighted) 82 89 dB Interchannel Isolation 80 95 dB Interchannel Gain Mismatch 0.2 0.5 dB Input Voltage (Note 3) 1.35 1.50 1.65 Vpp Input Resistance 50 100 k Power Supply Rejection (Note 4) 35 dB DAC Analog Output Characteristics: Resolution 20 Bits S/(N+D) 75 85 dB D-Range (-60dB Output, A-weighted) 86 92 dB S/N (A-weighted) 86 92 dB Interchannel Isolation 80 95 dB Interchannel Gain Mismatch 0.2 0.5 dB Output Voltage (Note 3) 1.35 1.50 1.65 Vpp Load Resistance 10 k Load Capacitance 30 pF Power Supply Rejection (Note 4) 50 dB Power Supplies Power Supply Current AD+DA AD DA Power down (Note 5) Power Consumption PWAD = "H", PWDA = "H" PWAD = "H", PWDA = "L" PWAD = "L", PWDA = "H" PWAD = "L", PWDA = "L" 10 5.6 5.6 10 15 8.4 8.4 50 mA mA mA uA
mW 37.5 25 PWAD = "H", PWDA = "H" AD+DA mW 21 14 AD PWAD = "H", PWDA = "L" mW 21 14 DA PWAD = "L", PWDA = "H" uW 125 25 PWAD = "L", PWDA = "L" Power down (Note 5) Note 2. The offset of ADC is removed by internal HPF. Note 3. Input /Output of ADC and DAC scales with VDD voltage. 0.6 X VDD (typ). Note 4. PSR is applied to VDD with 1kHz, 50mV. Note 5. In case of power-down mode, all digital input including clocks pins (MCLK, SCLK and LRCK) are held VDD or VSS. But PWAD and PWDA pins are held VSS.
MS0029-E-00 -4-
2000/5
ASAHI KASEI
[AK4551]
FILTER CHARACTERISTICS
(Ta=25C; VDD=2.2 3.6V; fs=44.1kHz; DEM0="1", DEM1="0") Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): 17.4 kHz PB 0 Passband (Note 6) 0.1dB kHz 20.0 -1.0dB kHz 21.1 -3.0dB Stopband SB 27.0 kHz Passband Ripple PR dB 0.1 Stopband Attenuation SA 65 dB Group Delay (Note 7) GD 17.0 1/fs Group Delay Distortion 0 us GD ADC Digital Filter (HPF): Hz FR 3.4 Frequency Response (Note 6) -3dB Hz 10 -0.5dB Hz 22 -0.1dB DAC Digital Filter: PB 0 20.0 kHz Passband (Note 6) 0.1dB 22.05 kHz -6.0dB Stopband SB 24.1 kHz Passband Ripple PR dB 0.06 Stopband Attenuation SA 43 dB Group Delay (Note 7) GD 15.4 1/fs Group Delay Distortion 0 us GD DAC Digital Filter + Analog Filter FR dB Frequency Response 0 20.0kHz 0.5 Note 6. The passband and stopband frequencies scale with fs (sampling frequency). For examples, PB=20.0kHz(@ADC: -1.0dB, DAC: -0.1dB) are 0.454 x fs. Note 7. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 20bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20bit data of both channels on input register to the output of analog signal.
DC CHARACTERISTICS
(Ta=25C; VDD=2.2 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-20uA) Low-Level Output Voltage (Iout=20uA) Input Leakage Current Symbol VIH VIL VOH VOL Iin min 70%VDD VDD-0.1 typ max 30%VDD 0.1 10 Units V V V V uA
MS0029-E-00 -5-
2000/5
ASAHI KASEI
[AK4551]
SWITCHING CHARACTERISTICS
(Ta=25C; VDD=2.2 3.6V; CL=20pF) Parameter Symbol min 2.048 fCLK Master Clock Timing 256fs: 28 tCLKL Pulse Width Low 28 tCLKH Pulse Width High 3.072 fCLK 384fs: 23 tCLKL Pulse Width Low 23 tCLKH Pulse Width High 4.096 fCLK 512fs: 16 tCLKL Pulse Width Low 16 tCLKH Pulse Width High fs 8 LRCK Frequency Duty Cycle 45 Serial Interface Timing SCLK Period 312.5 tSCK SCLK Pulse Width Low 130 tSCKL Pulse Width High 130 tSCKH 50 tLRS LRCK Edge to SCLK "" (Note 8) 50 tSLR SCLK "" to LRCK Edge (Note 8) tDLR LRCK Edge to SDTO (MSB) tDSS SCLK "" to SDTO 50 tSDH SDTI Hold Time 50 tSDS SDTI Setup Time Reset Timing PWAD or PWDA Pulse Width tPW 150 (Note 9) PWAD "" to SDTO Valid tPWV Note 8. SCLK rising edge must not occur at the same time as LRCK edge. Note 9. These cycles are the number of LRCK rising from PWAD rising. typ 11.2896 max 12.8 Units MHz ns ns MHz ns ns MHz ns ns kHz % ns ns ns ns ns ns ns ns ns ns 1/fs
16.9344
19.2
22.5792
25.6
44.1
50 55
80 80
2081
MS0029-E-00 -6-
2000/5
ASAHI KASEI
[AK4551]
n Timing Diagram
LRCK 50% VDD tSLR tLRS tSCKH tSCKL 50% VDD tDLR tDSS
SCLK
SDTO
50% VDD tSDS tSDH 50% VDD
SDTI
Serial Interface Timing
tPW 50%VDD tPW PWAD tPWV 50%VDD
PWDA
SDTO
Reset & Initialize Timing
MS0029-E-00 -7-
2000/5
ASAHI KASEI
[AK4551]
OPERATION OVERVIEW n System Clock Input
The AK4551 can be input MCLK=256fs, 384fs or 512fs. The input clock applied to the MCLK as internal master clock is divided into 256fs automatically. The relationship between the external clock applied to the MCLK input and the desired sample rate is defined in Table 1. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. *fs is sampling frequency. When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4551 may occur click noise. In case of DAC, click noise is avoided by setting the inputs to "0". All external clocks (MCLK, SCLK, LRCK) must be present unless PWAD and PWDA = "L". If these clocks are not provided, the AK4551 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally.
fs 32.0kHz 44.1kHz 48.0kHz
256fs 8.1920MHz 11.2896MHz 12.2880MHz
MCLK 384fs 12.2880MHz 16.9344MHz 18.4320MHz
512fs 16.3840MHz 22.5792MHz 24.5760MHz
SCLK 32fs 64fs 1.0240MHz 2.048MHz 1.4112MHz 2.822MHz 1.5360MHz 3.072MHz
Table 1. System Clock Example
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The data is MSB first, 2's compliment.
LRCK SCLK(i) (64fs) SDTO(o) SDTI(i)
0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1
19 18
8
7
6
0
19 18
8
7
6
0
19
Don't care 19:MSB, 0:LSB
19 18
12 11
1
0
Don't care
19 18
12 11
1
0
Lch Data
Figure 1. Audio Interface Timing
Rch Data
MS0029-E-00 -8-
2000/5
ASAHI KASEI
[AK4551]
n De-emphasis filter
The DAC of AK4551 includes the digital de-emphasis filter (tc=50/15us) by IIR filter. This filter corresponds to three frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled for input audio data. The de-emphasis is also disabled at DEM0="1" and DEM1="0". DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 2. De-emphasis filter control
n Digital High Pass Filter
The AK4551 has a Digital High Pass Filter (HPF) for DC-offset cancel. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz and the frequency response at 20Hz is -0.12dB. It also scales with the sampling frequency (fs).
MS0029-E-00 -9-
2000/5
ASAHI KASEI
[AK4551]
n Power-down & Reset
The ADC and DAC of AK4551 are placed in the power-down mode by bringing each power down pin, PWAD , PWDA = "L" independently and each digital filter is also reset at the same time. These resets should always be done after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 2 shows the power-up sequence when the ADC is powered up before the DAC power-up.
PWAD
2081/fs
ADC Internal State PWDA
Normal Operation
Power-down
Init Cycle
Normal Operation
DAC Internal State
Normal Operation GD
Power-down
Normal Operation GD
ADC In (Analog) ADC Out (Digital) DAC In (Digital)
GD
Idle Noise
"0"data
Idle Noise
"0"data GD
DAC Out (Analog) Clock In
MCLK,LRCK,SCLK
The clocks may be stopped.
External Mute
Mute ON
Figure 2. Power-up Sequence
MS0029-E-00 - 10 -
2000/5
ASAHI KASEI
[AK4551]
SYSTEM DESIGN
Figure 3 shows the system connection diagram. An evaluation board [AKD4551] is available which demonstrates application circuit, optimum layout, power supply arrangements and measurement results.
+
4.7u 470
0.1u
Rch In
+ 2.2n
1
470
VCOM AINR AINL VSS VDD DEM0 DEM1 SDTO
AOUTR 16 AOUTL 15
Lch In
+ 2.2n
2 3 4
0.1u
Analog Supply 2.2 3.6V
AK4551
Top View
PWDA PWAD
14 13
Reset Reset
10u
+
5 6 7 8
SCLK 12 MCLK 11 LRCK 10 SDTI 9
Controller
Mode Control
Analog Ground
System Ground
Figure 3. System Connection Diagram Example Notes: - LRCK=fs, 40fs SCLK 96fs, MCLK=256fs/384fs/512fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.
MS0029-E-00 - 11 -
2000/5
ASAHI KASEI
[AK4551]
1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitors should be as near to the AK4551 as possible, with the small value ceramic capacitor being nearest. 2. Voltage Reference The input to VDD voltage sets the analog input/output range. A 0.1uF ceramic capacitor and a 10uF electrolytic capacitor is connected to VDD and VSS pins, normally. VCOM is a signal ground of this chip. An electrolytic less than 4.7uF in parallel with a 0.1uF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from the VDD, VCOM pins in order to avoid unwanted coupling into the AK4551. 3. Analog Inputs ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and nominally 0.6xVDD Vpp(typ). The ADC output data format 2's compliment. The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below a negative full scale. The ideal code is 00000H (@20bit) with no input signal. The AK4551 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs. 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6xVDD Vpp(typ). The DAC input data format is 2's compliment. The output voltage is a positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). If the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
MS0029-E-00 - 12 -
2000/5
ASAHI KASEI
[AK4551]
n Layout Pattern Example
AK4551 requires careful attention to power supply and grounding arrangements to optimize performance. (Please refer to AKD4551 Evaluation Board layout pattern.) 1. VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog ground on system. The AK4551 is placed on the analog ground plane, and near the analog ground and digital ground split. And analog and digital ground planes should be only connected at one point. The connection point should be near to the AK4551. VDD pin should be distributed from the point with low impedance of regulator etc. The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise coupling to analog circuit in the AK4551, a 10pF ceramic capacitor on MCLK pin is connected with digital ground. 0.1uF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4551 as possible. And these lines should be the shortest connection to pins.
2. 3.
4.
4.7u
+
0.1u
Rch In
+
470 2.2n
1 VCOM Lch In
+ 470 2.2n
AOUTR 16 AOUTL 15
2 AINR 3 AINL 4 VSS
Analog Supply 2.2 3.6V
AK4551
Top View
PWDA
14
PWAD 13
51
Reset &Power-down
+ 10u 0.1u
5 VDD 6 DEM0 7 DEM1 8 SDTO
SCLK 12 MCLK 11 LRCK 10 SDTI 9
51 51 10P 51
Controller
Analog Ground
Digital Ground Mode Control
51
Figure 4. Layout Pattern Example
MS0029-E-00 - 13 -
2000/5
ASAHI KASEI
[AK4551]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 1.0 0.10 0-10
Epoxy Cu Solder plate 2000/5 - 14 -
1 0.220.1
8 0.65
Seating Plane
NOTE: Dimension "*" does not include mold flash.
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0029-E-00
*4.4
ASAHI KASEI
[AK4551]
MARKING
AKM 4551VT XXYYY
1) 2)
3) 4)
Pin #1 indication Date Code : XXYYY (5 digits) XX: lot# YYY: Date Code Marketing Code : 4551VT Asahi Kasei Logo
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0029-E-00 - 15 -
2000/5

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